Abstract. Complex real time systems like large system on chips need to be verified to assure 
quality and save time. Today verification activities are re-stricted to the register transfer 
level or one design step above. A complete flow from early specifications down to physical 
implementation is still not available. An improved system level design cycle is required to 
overcome this limitation. In this paper we propose an extended methodology of the system level 
design cycle to support early validation and formal verification of temporal properties in 
system specifications.